Conventional way to generate a low jitter clock at high data rates is to use an LC (inductor-capacitor) oscillator. While LC oscillators may achieve very low jitter, the inductor required can occupy a large area depending on the desired frequency of oscillation. For a serializer/de-serializer application with many lanes on a chip, VCO (voltage controlled oscillator) pulling can become a concern when inductors are in close proximity. VCO pulling is an effect which is realized when one oscillator can affect the oscillation frequency of another oscillator. While techniques are known to overcome this problem, these techniques occupy additional area and degrade performance. In addition, LC-VCO center frequency can be process-dependent, requiring respins when the VCO frequency is higher or lower than targeted. A “respin” is an additional manufacturing run in which the design is slightly changed, in this case so that a certain performance characteristic can be achieved. Generally, respins are to be avoided since they delay product readiness.